1. Field of the Invention
Generally, the present disclosure relates to highly sophisticated integrated circuits including transistor elements having triple gate architecture (FinFET).
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, on the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and thus allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is prefer-ably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. The relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for performance driven circuits.
For this reason, superior gate electrode structures have been developed in which new gate dielectric materials may be implemented, possibly in combination with additional electrode materials, in order to provide superior capacitive coupling between the gate electrode and the channel region, while at the same time maintaining the resulting leakage currents at a low level. To this end, so-called high-k dielectric materials may frequently be used, which are to be understood as dielectric materials having a dielectric constant of 10.0 and higher. For example, a plurality of metal oxides or silicates may be used, possibly in combination with conventional very thin dielectric materials, in order to obtain sophisticated high-k metal gate electrode structures. For example, in some well-established approaches, the gate electrode structures of planar transistors may be formed on the basis of well-established concepts, i.e., using conventional gate dielectrics and polysilicon material, wherein the sophisticated material systems may then be incorporated in a very late manufacturing stage, i.e., prior to forming any metallization systems and after completing the basic transistor configuration by replacing the polysilicon material with the high-k dielectric material and appropriate gate electrode materials. Consequently, in any such replacement gate approaches, well-established process techniques and materials may be used for forming the basic transistor configurations, while in a late manufacturing stage, i.e., after performing any high temperature processes, the sophisticated gate materials may be incorporated.
In view of further device scaling and possibly based on well-established materials, new transistor configurations have been proposed in which a “three dimensional” architecture is provided in an attempt to obtain a desired channel width, while at the same time superior controllability of the current flow through the channel region is preserved. To this end, so-called FinFETs have been proposed in which a thin sliver of thin silicon is formed in a thin active layer of a silicon-on-insulator (SOI) substrate, wherein on both sidewalls and, if desired, on a top surface, a gate dielectric material and a gate electrode material are provided thereby realizing a multiple gate transistor whose channel region may be fully depleted. Typically, in sophisticated applications, the width of the silicon fins is on the order of magnitude of 10-20 nm and the height thereof is on the order of magnitude of 30-40 nm. In some conventional approaches for forming FinFETs, the fins are formed as elongated device features followed by the deposition of the gate electrode materials, possibly in combination with any spacers, and thereafter the end portions of the fins may be “merged” by epitaxially growing a silicon material, which may result in complex manufacturing processes, thereby also possibly increasing the overall external resistance of the resulting drain and source regions.
In further attempts to provide FinFETs on the basis of a bulk configuration, it has been proposed to form semiconductor fins in a bulk substrate on the basis of a self-aligned process strategy in which a gate opening is defined by an appropriate etch mask formed above the semiconductor material. In a further step, the opening is patterned by complex lithography techniques so as to obtain a further mask, which may define the lateral position and size of the fins, which may subsequently be formed on the basis of complex patterning strategies. Thereafter, an appropriate dielectric material such as silicon dioxide may be filled into the resulting structure in order to appropriately adjust the electrical effective height of the previously etched fins. Although this approach may represent a promising manufacturing technique, a complex process strategy may have to be applied prior to actually patterning the gate electrode in order to form the fins in the gate opening and adjusting their effective electrical height.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.